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DC-20 GHz 5-BIT CMOS digital step attenuator with low insertion loss and phase error
- Authors
- Cho, Moon-Kyu; Baek, Donghyun; Kim, Jeong-Geun
- Issue Date
- Apr-2013
- Publisher
- WILEY-BLACKWELL
- Keywords
- CMOS; digital step attenuator; single-pole double-throw (SPDT); double-pole double-throw (DPDT); phase error
- Citation
- MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, v.55, no.4, pp 762 - 764
- Pages
- 3
- Journal Title
- MICROWAVE AND OPTICAL TECHNOLOGY LETTERS
- Volume
- 55
- Number
- 4
- Start Page
- 762
- End Page
- 764
- ISSN
- 0895-2477
1098-2760
- Abstract
- This article presents a 5-bit broadband digital step attenuator with low insertion loss and phase error using a standard 0.13 m CMOS process for the phased array antenna.The maximum attenuation of 31 dB with the LSB of 1 dB is achieved at DC-20 GHz. The measured insertion loss of the reference state is <11 dB and the input and output return losses are <10 dB at DC-20 GHz. The root mean square (RMS) phase and amplitude errors are <2.5 degrees and <0.7 dB, respectively. The current consumption is near zero with 1.2 V supply. The chip size is 1.04 x 0.48 mm2 including pads. (c) 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:762764, 2013; View this article online at wileyonlinelibrary.com. DOI: 10.1002/mop.27448
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