Design Optimization of InAs-Based Gate-All-Around (GAA) Arch-Shaped Tunneling Field-Effect Transistor (TFET)

Abstract

In this work, an InAs-based gate-all-around (GAA) arch-shaped tunneling field-effect transistor (TFET) was designed and analyzed using technology computer-aided design (TCAD) simulations. To progress the DC/RF characteristics of GAA arch-shaped TFET, InAs, a highly attractive III-V compound material, is adopted as a channel material. Owing to the GAA arch-shaped structure of TFET, the tunneling region under the gate area is extended, and the on-state current (I-on) and subthreshold-swing (S) are improved. However, it has some performance limitations that are related to the height of the source region (H-source) and the epitaxially grown thickness of the channel (t(epi)). Thus, we performed a design optimization of the InAs-based GAA arch-shaped TFET with the variables H-source and t(epi). After the optimization process, RF characteristics such as gate capacitance, transconductance (g(m)), cutoff frequency (f(T)), and maximum oscillation frequency (f(max)) were extracted and analyzed by small-signal RF modeling. Finally, the designed InAs-based GAA arch-shaped TFET demonstrated an I-on of 10.6 mA/mu m, S of 6.5 mV/dec, f(T) of 2.3 THz, and f(max) of 20 THz.