A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS
DC Field | Value | Language |
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dc.contributor.author | Yoo, Taegeun | - |
dc.contributor.author | Yeoh, Hong Chang | - |
dc.contributor.author | Jung, Yun-Hwan | - |
dc.contributor.author | Cho, Seong-Jin | - |
dc.contributor.author | Kim, Yong Sin | - |
dc.contributor.author | Kang, Sung-Mo | - |
dc.contributor.author | Baek, Kwang-Hyun | - |
dc.date.available | 2019-05-28T11:32:37Z | - |
dc.date.issued | 2014-12 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.issn | 1558-173X | - |
dc.identifier.uri | https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/19082 | - |
dc.description.abstract | This paper presents a direct digital frequency synthesizer (DDFS) based on the nonlinear DAC with a maximum operating frequency of 2 GHz. This work proposes three design methods to enhance the performance of a DDFS. First, a multi-level momentarily activated bias is proposed to reduce power dissipation in the phase accumulator. Second, a coarse phase-based consecutive fine amplitude grouping scheme is presented to reduce hardware complexity and power consumption in the digital decoder. Third, the mixed-wave conversion topology in the nonlinear DAC is proposed to improve the output spectral purity. The DDFS with 9 bit amplitude resolution is capable of producing a minimum spurious-free dynamic range (SFDR) of 55.1 dBc up to Nyquist frequency at the clock frequency of 2 GHz. The prototype DDFS is fabricated in a 55-nm CMOS. It occupies an active area of 0.1 mm(2) with a total power dissipation of 130 mW. The figure of merit of this DDFS is 8944 GHz . 2((SFDR/6))/W. | - |
dc.format.extent | 14 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/JSSC.2014.2359674 | - |
dc.identifier.bibliographicCitation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.49, no.12, pp 2976 - 2989 | - |
dc.description.isOpenAccess | N | - |
dc.identifier.wosid | 000345620100021 | - |
dc.identifier.scopusid | 2-s2.0-84913603591 | - |
dc.citation.endPage | 2989 | - |
dc.citation.number | 12 | - |
dc.citation.startPage | 2976 | - |
dc.citation.title | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.citation.volume | 49 | - |
dc.type.docType | Article; Proceedings Paper | - |
dc.publisher.location | 미국 | - |
dc.subject.keywordAuthor | Direct digital frequency synthesizer (DDFS) | - |
dc.subject.keywordAuthor | digital-to-analog converter (DAC) | - |
dc.subject.keywordAuthor | segmented nonlinear DAC | - |
dc.subject.keywordAuthor | phase accumulator | - |
dc.subject.keywordAuthor | CMOS current mode logic | - |
dc.subject.keywordPlus | PIPELINED PHASE ACCUMULATOR | - |
dc.subject.keywordPlus | INP DHBT TECHNOLOGY | - |
dc.subject.keywordPlus | 0.18-MU-M SIGEBICMOS TECHNOLOGY | - |
dc.subject.keywordPlus | SINE-WEIGHTED DAC | - |
dc.subject.keywordPlus | MU-M CMOS | - |
dc.subject.keywordPlus | CLOCK FREQUENCY | - |
dc.subject.keywordPlus | ROM | - |
dc.subject.keywordPlus | PERFORMANCE | - |
dc.subject.keywordPlus | DDFSS | - |
dc.subject.keywordPlus | APPROXIMATION | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | sci | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
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