A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS
- Authors
- Yoo, Taegeun; Yeoh, Hong Chang; Jung, Yun-Hwan; Cho, Seong-Jin; Kim, Yong Sin; Kang, Sung-Mo; Baek, Kwang-Hyun
- Issue Date
- Dec-2014
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Direct digital frequency synthesizer (DDFS); digital-to-analog converter (DAC); segmented nonlinear DAC; phase accumulator; CMOS current mode logic
- Citation
- IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.49, no.12, pp 2976 - 2989
- Pages
- 14
- Journal Title
- IEEE JOURNAL OF SOLID-STATE CIRCUITS
- Volume
- 49
- Number
- 12
- Start Page
- 2976
- End Page
- 2989
- URI
- https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/19082
- DOI
- 10.1109/JSSC.2014.2359674
- ISSN
- 0018-9200
1558-173X
- Abstract
- This paper presents a direct digital frequency synthesizer (DDFS) based on the nonlinear DAC with a maximum operating frequency of 2 GHz. This work proposes three design methods to enhance the performance of a DDFS. First, a multi-level momentarily activated bias is proposed to reduce power dissipation in the phase accumulator. Second, a coarse phase-based consecutive fine amplitude grouping scheme is presented to reduce hardware complexity and power consumption in the digital decoder. Third, the mixed-wave conversion topology in the nonlinear DAC is proposed to improve the output spectral purity. The DDFS with 9 bit amplitude resolution is capable of producing a minimum spurious-free dynamic range (SFDR) of 55.1 dBc up to Nyquist frequency at the clock frequency of 2 GHz. The prototype DDFS is fabricated in a 55-nm CMOS. It occupies an active area of 0.1 mm(2) with a total power dissipation of 130 mW. The figure of merit of this DDFS is 8944 GHz . 2((SFDR/6))/W.
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Collections - College of ICT Engineering > School of Electrical and Electronics Engineering > 1. Journal Articles
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