Physical Parameter-Based SPICE Models for InGaZnO Thin-Film Transistors Applicable to Process Optimization and Robust Circuit Design
DC Field | Value | Language |
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dc.contributor.author | Kim, Dae Hwan | - |
dc.contributor.author | Jeon, Yong Woo | - |
dc.contributor.author | Kim, Sungchul | - |
dc.contributor.author | Kim, Yongsik | - |
dc.contributor.author | Yu, Yun Seop | - |
dc.contributor.author | Kim, Dong Myong | - |
dc.contributor.author | Kwon, Hyuck-In | - |
dc.date.available | 2019-05-29T09:07:00Z | - |
dc.date.issued | 2012-01 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.issn | 1558-0563 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/20598 | - |
dc.description.abstract | In this letter, we show that the physics-based equation that was derived for amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) in our previous work can be successfully incorporated into the SPICE model via Verilog-A. The proposed model and extracted SPICE parameters successfully reproduce the measured current-voltage characteristics of amorphous indium-gallium-zinc-oxide (a-IGZO) TFTs and the load line diagram of a-IGZO TFT inverters. The main advantage of our model is that each parameter has its physical meaning and most of them can be related with the fabrication conditions of AOS TFTs. To show the advantage of the proposed models and extracted SPICE parameters more clearly, we investigate the effect of ionized donor concentration (N-D(+)) on the inverter circuit operation and determine the optimum value of N-D(+) and device dimensions considering the tradeoff between the power consumption and the output swing in a-IGZO inverters. The proposed physics-based SPICE model via Verilog-A is expected to play a significant role in the process optimization and circuit design with AOS TFTs. | - |
dc.format.extent | 3 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Physical Parameter-Based SPICE Models for InGaZnO Thin-Film Transistors Applicable to Process Optimization and Robust Circuit Design | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/LED.2011.2172184 | - |
dc.identifier.bibliographicCitation | IEEE ELECTRON DEVICE LETTERS, v.33, no.1, pp 59 - 61 | - |
dc.description.isOpenAccess | N | - |
dc.identifier.wosid | 000298380300019 | - |
dc.identifier.scopusid | 2-s2.0-84655164769 | - |
dc.citation.endPage | 61 | - |
dc.citation.number | 1 | - |
dc.citation.startPage | 59 | - |
dc.citation.title | IEEE ELECTRON DEVICE LETTERS | - |
dc.citation.volume | 33 | - |
dc.type.docType | Article | - |
dc.publisher.location | 미국 | - |
dc.subject.keywordAuthor | Amorphous indium-gallium-zinc-oxide (a-IGZO) | - |
dc.subject.keywordAuthor | amorphous oxide semiconductor (AOS) | - |
dc.subject.keywordAuthor | inverter | - |
dc.subject.keywordAuthor | SPICE | - |
dc.subject.keywordAuthor | thin-film transistor (TFT) | - |
dc.subject.keywordAuthor | Verilog-A | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | sci | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
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