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낮은 Subthreshold 누설전류를 갖는 CMOS 논리회로
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 송상헌 | - |
| dc.date.available | 2019-07-16T05:00:29Z | - |
| dc.date.issued | 2004-10 | - |
| dc.identifier.issn | 1229-246X | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/28534 | - |
| dc.description.abstract | We propose a new method to reduce the subthreshold leakage current. By moving the operating point of OFF state MOSFETs through input-controlled voltage generators, logic circuits with much lower leakage current can be built with few extra components. SPICE simulation results for the new inverter show correct logic results without speed degradation compared to a conventional inverter. | - |
| dc.format.extent | 5 | - |
| dc.publisher | 대한전기학회 | - |
| dc.title | 낮은 Subthreshold 누설전류를 갖는 CMOS 논리회로 | - |
| dc.title.alternative | CMOS Logic Circuits with Lower Subthreshold Leakage Current | - |
| dc.type | Article | - |
| dc.identifier.bibliographicCitation | 전기학회논문지 C권, v.53, no.10-C, pp 500 - 504 | - |
| dc.identifier.kciid | ART001182558 | - |
| dc.description.isOpenAccess | N | - |
| dc.citation.endPage | 504 | - |
| dc.citation.number | 10-C | - |
| dc.citation.startPage | 500 | - |
| dc.citation.title | 전기학회논문지 C권 | - |
| dc.citation.volume | 53 | - |
| dc.subject.keywordAuthor | CMOS | - |
| dc.subject.keywordAuthor | Subthreshold | - |
| dc.subject.keywordAuthor | Leakage Current | - |
| dc.subject.keywordAuthor | Logic Circuit | - |
| dc.subject.keywordAuthor | Inverter | - |
| dc.description.journalRegisteredClass | kci | - |
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