VLSI Implementation of High Throughput Turbo Decoder for Mobile WiMAX Modem
- Authors
- 오상목; 이정우
- Issue Date
- 2009
- Keywords
- Turbo decoder; mobile WiMAX; VLSI implementation; throughput; operating frequency
- Citation
- Telecommunications Review, v.19, no.5, pp 786 - 801
- Pages
- 16
- Journal Title
- Telecommunications Review
- Volume
- 19
- Number
- 5
- Start Page
- 786
- End Page
- 801
- URI
- https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/33329
- ISSN
- 1226-5586
- Abstract
- In this paper, we propose the architecture for the high-throughput turbo (CTC) decoder used in the Mobile WiMAX
modem. The proposed CTC decoder uses Min-Log-MAP algorithm, unsigned bits for quantization of metrics, and
efficient architecture for finding a minimum value and preventing overflows in the computation of state metrics.
Instead of using two stages of comparators to find a minimum value, which is conventional in the state metric
computation unit, the proposed CTC decoder replaces the second stage of comparators by AND gates for the Most
Significant Bits (MSB) of the first stage outputs. Thanks to the reduction of the complexity resulting from the efficient
architecture, the CTC decoder achieves high operating frequency. The proposed CTC decoder architecture allows
parallel computation of forward state metrics and backward state metrics. As a result, the number of cycles required to
complete one iteration of decoding are reduced by half compared with those of conventional CTC decoders. A
permuter, used as interleaver and deinterleaver alternatively, is designed to reduce by half the cycle required for data
writing and thus to be compatible with the parallel computation of state metrics. The proposed CTC decoder is
implemented by Samsung 0.18um CMOS process. A single CTC decoder designed by proposed architecture supports
the operating frequency of 275 MHz and the throughput of 68.3 Mbps. It is verified that the throughput requirement of
Mobile WiMAX standard is satisfied by using two CTC decoders in a parallel manner.
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