Balanced sampling switch for high linearity and a wide temperature range in low power SAR ADCs
- Authors
- Kim, J. E.; Yoo, T.; Baek, K. -H.; Kim, T. T. -H.
- Issue Date
- Nov-2019
- Publisher
- INST ENGINEERING TECHNOLOGY-IET
- Keywords
- digital-analogue conversion; leakage currents; analogue-digital conversion; low-power electronics; switches; sampling methods; CMOS digital integrated circuits; low power SAR ADCs; balanced sampling switch technique; NMOS sampling switch; hold mode; main SAR conversion; conventional sampling switch; mini C-DAC; leakage current reduction; mini capacitive digital-to-analogue converter; SAR conversion; temperature 120; 0 degC; voltage 0; 5 V; word length 10 bit
- Citation
- ELECTRONICS LETTERS, v.55, no.24, pp 1273 - 1274
- Pages
- 2
- Journal Title
- ELECTRONICS LETTERS
- Volume
- 55
- Number
- 24
- Start Page
- 1273
- End Page
- 1274
- URI
- https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/37412
- DOI
- 10.1049/el.2019.2533
- ISSN
- 0013-5194
1350-911X
- Abstract
- This Letter proposes a balanced sampling switch technique for achieving high linearity and a wide temperature range. The proposed technique reduces the V-DS of the NMOS sampling switch for reducing the leakage current through the switch during the hold mode. This operation is implemented by a mini capacitive digital-to-analogue converter (C-DAC) that mimics the main C-DAC used for main SAR conversion. The proposed sampling switch is applied to a 10-bit, 0.5 V SAR ADC with 5 Msample/s and verified by comprehensive simulation. Compared to the conventional sampling switch without the mini C-DAC, the proposed switch improves SFDR and SNDR by 27.52 dBc and 11.8 dB, respectively, at the FF corner and 120 degrees C.
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Collections - College of ICT Engineering > School of Electrical and Electronics Engineering > 1. Journal Articles
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