Detailed Information
Cited 0 time in 
Cited 0 time in 
Cited 0 time in
Metadata Downloads
A Diacnosable Network-on-Chip for FPGA Verification of Intellectual Properties
- Authors
- Han, Kyuseung; Lee, Jae-Mu; Lee, Woojoo; Lee, Jinho
- Issue Date
- Mar-2019
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- debugging; FPGA verification; Network-on-chip
- Citation
- IEEE DESIGN & TEST, v.36, no.2, pp 81 - 87
- Pages
- 7
- Journal Title
- IEEE DESIGN & TEST
- Volume
- 36
- Number
- 2
- Start Page
- 81
- End Page
- 87
- ISSN
- 2168-2356
- Abstract
- Editor's note: Debug and validation are important steps required to ensure that systems-on-chip satisfies the design specs. This article presents an elegant diagnosis technique integrated within the network-on-chip infrastructure. The authors demonstrate the proposed technique on an FPGA prototype.-Umit Y. Ogras, Arizona State University © 2013 IEEE.
- Files in This Item
- There are no files associated with this item.
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.