A 0.007 mm 0.6 V 6 MS/s Low-Power Double Rail-to-Rail SAR ADC in 65-nm CMOS
- Authors
- Jo, Y.; Kim, J.E.; Baek, K.; Kim, T.T.
- Issue Date
- Sep-2021
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- Capacitors; Circuits and systems; compute-in-memory; double rail-to-rail; low-power; Parasitic capacitance; power-efficient.; Redundancy; SAR ADC; Signal to noise ratio; Switches; Transistors
- Citation
- IEEE Transactions on Circuits and Systems II: Express Briefs, v.68, no.9, pp 3088 - 3092
- Pages
- 5
- Journal Title
- IEEE Transactions on Circuits and Systems II: Express Briefs
- Volume
- 68
- Number
- 9
- Start Page
- 3088
- End Page
- 3092
- URI
- https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/48976
- DOI
- 10.1109/TCSII.2021.3097126
- ISSN
- 1549-7747
1558-3791
- Abstract
- A 0.007mm 0.6V 6MS/s 10b double rail-to-rail input range SAR ADC is implemented in 65-nm technology. The extended input range broadens the applications of the low-power SAR ADCs such as compute-in-memory. The proposed ADC occupies less area since it only needs additional two seriesconnected capacitors and a differential-difference comparator for double rail-to-rail operation. The set-and-down operation reduces the input-referred noise of the comparator by over ten times than complementary switching. The novel metal-insulator-metal and metal-oxide-metal capacitor hybrid cap-DAC architecture minimize the gain error of ADC. The prototype achieves SNR of 53.90-dB, SNDR of 52.12-dB, and SFDR of 60.39-dB, power of 12.98-muW, and FoM of 6.6-fJ/conv.-step.
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Collections - College of ICT Engineering > School of Electrical and Electronics Engineering > 1. Journal Articles
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