A 10-bit, 50 MS/s, 55 fJ/conversion-step SAR ADC with split capacitor array

Abstract

In this paper, a split capacitor array structure for successive approximation register (SAR) ADC is proposed. By connecting the node of upper plate of LSB capacitor arrays to the reference voltage while MSB operation is activated, the proposed ADC can alleviate the problem of parasitic capacitance without using extra calibration circuitry and conversion cycles. The proposed ADC is designed using 0.13-um 1P6M CMOS technology. At a 1.2-V supply and 50 MS/s, the ADC achieves an SNDR of 56.9 dB and consumes 1.58 mW, resulting in a figure of merit (FOM) of 55 fJ/conversion-step. The ADC core occupies an active area of 350 × 440 um 2.