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A 1.3GHz 350mW Hybrid Direct Digital Frequency Synthesizer in 90nm CMOS
- Issue Date
- 2009
- Publisher
- JAPAN SOCIETY APPLIED PHYSICS
- Citation
- 2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, pp 122 - 123
- Pages
- 2
- Journal Title
- 2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS
- Start Page
- 122
- End Page
- 123
- ISSN
- 0000-0000
- Abstract
- This paper presents a low power hybrid direct digital frequency synthesizer (DDFS) with a maximum operating frequency of 1.3GHz fabricated in 90nm CMOS. The proposed hybrid design extends the resolution of the nonlinear DAC by adding a linear slope component to the sine approximation via an additional linear DAC. With an 11-bit combined DAC, this DDFS produces a minimum SFDR of 52dBc up to Nyquist at 1.3GHz while dissipating only 350mW and occupying 2mm(2) including pads. The FOM of this chip is measured at 1207.9GHz.2(ENOB)/W.
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Related Researcher
- Baek, Kwang Hyun
- 창의ICT공과대학 (전자전기공학부)