A flexible tradeoff between code size and WCET using a dual instruction set processor

Abstract

Embedded systems are often constrained in terms of both code size and execution time, due to a limited amount of available memory and real-time nature of applications. A dual instruction set processor, which supports a reduced instruction set (16 bits/instruction) in addition to a full instruction set (32 bits/instruction), allows an opportunity for a tradeoff between these two performance criteria. Specifically, while the reduced instruction set can be used to reduce code size by providing smaller instructions, a program compiled into the reduced instruction set typically runs slower than the same program compiled into the full instruction set. Motivated by this observation, we propose a code generation technique that exploits this tradeoff relationship by selectively using the two instruction sets for different sections in the program. The proposed technique not only provides a mechanism to enable a flexible tradeoff between a program's code size and its execution time, but also optimizes the program towards enhancing its WCET (worst case execution time). The results from our experiments show that our proposed technique can be effectively used to fine-tune an application program on a spectrum of code size and worst case performance, which in turn enables a system-wide optimization on memory space and execution speed involving multiple applications.