Design and implementation of efficient cipher engine for IEEE 802.11i compatible with IEEE 802.11n and IEEE 802.11e

Abstract

For high data rate, new MAC mechanisms such as Block Ack in IEEE 802.11e and frame aggregation in IEEE 802.11n are being currently discussed and these mechanisms need short response time in each MPDU processing. In this paper, we propose a design of cipher engine for IEEE 802.11i to support these new mechanisms. We reduce the processing overhead of RC4 key scheduling by means of using the dual S-Box scheme. In CCMP design, parallel structure is proposed, and as a result, we reduce the processing time to 1/2 in comparison with the sequential structure and the response time independent of the size of the payload and only dependent on the clock frequency. In addition, we can expect to decrease power consumption in CMOS design process because the clock frequency reduces to 1/5 and the area doubles compared to the typical designs.