A 0.5 V 10 b 3 MS/s 2-Then-1b/Cycle SAR ADC With Digital-Based Time-Domain Reference and Dual-Mode Comparator
- Authors
- Jung, Dong-Kyu; Seong, Kiho; Han, Jae-Soub; Shim, Yong; Baek, Kwang-Hyun
- Issue Date
- Mar-2022
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- SAR ADC; low-power; small-area; 2-then-1b; cycle conversion; time-domain reference; dual-mode comparator
- Citation
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.69, no.3, pp 909 - 913
- Pages
- 5
- Journal Title
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
- Volume
- 69
- Number
- 3
- Start Page
- 909
- End Page
- 913
- URI
- https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/57690
- DOI
- 10.1109/TCSII.2021.3125780
- ISSN
- 1549-7747
1558-3791
- Abstract
- This brief presents a low-power asynchronous 10-bit 2-then-1b/cycle successive approximation register (SAR) analog-to-digital converter (ADC). With partial adoption of 2b/cycle mode only for higher-order bit conversions, additional area and power consumption could be minimized while maintaining fast conversion rate. Moreover, unlike the previous 2b/cycle conversion architecture, where two capacitive digital-to-analog converters (C-DACs) and multiple analog comparators are unavoidable, the proposed 2-then-1b/cycle conversion is implemented with only one C-DAC and one analog comparator by utilizing a digital-based time-domain reference. The speed of 1b/cycle conversion for lower-order bits is improved with a dual-mode comparator. With the aforementioned techniques, the prototype 10-bit SAR ADC is fabricated in 65 nm CMOS process. The ADC core occupies an active area of 0.0142 mm(2) and consumes power of 3.8 mu W at 0.5 V supply voltage and 3 MS/s conversion rate. The SNDR measured at a Nyquist-rate input frequency is 56.41 dB, resulting in a figure of merit (FoM) is 2.33 fJ/c.-s.
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