Issues of advanced architectural features in the design of a timing tool
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Rhee, Byung-Do | - |
dc.contributor.author | Min, Sang Lyul | - |
dc.contributor.author | Lim, Sung-Soo | - |
dc.contributor.author | Shin, Heonshik | - |
dc.contributor.author | Kim, Chong Sang | - |
dc.contributor.author | Park, Chang Yun | - |
dc.date.accessioned | 2023-02-15T09:53:21Z | - |
dc.date.available | 2023-02-15T09:53:21Z | - |
dc.date.issued | 1994-05 | - |
dc.identifier.issn | 0000-0000 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/60672 | - |
dc.description.abstract | This paper describes a timing tool being developed by a real-time research group at Seoul National University. Our focus is on the issues resulting from advanced architectural features such as pipelined execution and cache memories found in many modern RISC-style processors. For each architectural feature we state the issues and explain our approach. | - |
dc.format.extent | 4 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | Publ by IEEE, Los Alamitos, CA, United States | - |
dc.title | Issues of advanced architectural features in the design of a timing tool | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/RTOSS.1994.292560 | - |
dc.identifier.bibliographicCitation | Proceedings of the IEEE Workshop on Real-Time Operating Systems and Software, pp 59 - 62 | - |
dc.description.isOpenAccess | N | - |
dc.identifier.scopusid | 2-s2.0-0028054548 | - |
dc.citation.endPage | 62 | - |
dc.citation.startPage | 59 | - |
dc.citation.title | Proceedings of the IEEE Workshop on Real-Time Operating Systems and Software | - |
dc.type.docType | Conference Paper | - |
dc.description.journalRegisteredClass | scopus | - |
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