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Issues of advanced architectural features in the design of a timing tool
- Authors
- Rhee, Byung-Do; Min, Sang Lyul; Lim, Sung-Soo; Shin, Heonshik; Kim, Chong Sang; Park, Chang Yun
- Issue Date
- May-1994
- Publisher
- Publ by IEEE, Los Alamitos, CA, United States
- Citation
- Proceedings of the IEEE Workshop on Real-Time Operating Systems and Software, pp 59 - 62
- Pages
- 4
- Journal Title
- Proceedings of the IEEE Workshop on Real-Time Operating Systems and Software
- Start Page
- 59
- End Page
- 62
- ISSN
- 0000-0000
- Abstract
- This paper describes a timing tool being developed by a real-time research group at Seoul National University. Our focus is on the issues resulting from advanced architectural features such as pipelined execution and cache memories found in many modern RISC-style processors. For each architectural feature we state the issues and explain our approach.
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