A Study on SRAM Designs to Exploit the TEI-aware Ultra-low Power Techniques

Abstract

Recently, temperature effect inversion aware ultra low power (TEI-ULP) techniques have been actively proposed to realize lower power above the existing ULP system-on-chips (SoCs) by utilizing the TEI phenomenon. Although these TEI-ULP techniques have been proven to have a significant power saving effect by applying them to logic parts in the actually fabricated SoC, SRAM has unfortunately been excluded from the benefits. This is because there has been no research on whether the TEI phenomenon occurs in ultra low voltage operating SRAM (ULV-SRAM) and, if so, whether the effect appears when TEI-ULP techniques are applied. In this paper, it is revealed for the first time that the TEI phenomenon occurs in the existing ULV-SRAM. In addition, this paper considers the stability problem of SRAM, which makes it difficult to apply the existing TEI-ULP techniques to ULV-SRAM, and proposes TEI-VSUS, a state-of-the-art TEI-ULP techniques to address this problem. Subsequently, this paper verifies the proposed TEI-VSUS in ULV-SRAM through intensive simulations, and the power saving rate for three representative ULV-SRAM models with different operations are acquired. Furthermore, an method to increase the power saving effect of TEIVSUS is proposed by relaxing the restrictions on stability so that the proposed technique can be used in a wider environment. The efficacy of the proposed method is also validated through simulations based on the ULV-SRAM models with the 28 nm FD-SOI process technology.