K-means Clustering-specific Lightweight RISC-V processor
- Authors
- Lee, W.; Park, J.; Byun, C.; Choi, E.; Lee, J.-H.; Lee, W.; Byun, K.J.; Han, K.
- Issue Date
- Oct-2021
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- acclerator; K-means clustering; RISC-V processor
- Citation
- Proceedings - International SoC Design Conference 2021, ISOCC 2021, pp 391 - 392
- Pages
- 2
- Journal Title
- Proceedings - International SoC Design Conference 2021, ISOCC 2021
- Start Page
- 391
- End Page
- 392
- URI
- https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/62138
- DOI
- 10.1109/ISOCC53507.2021.9613863
- ISSN
- 0000-0000
- Abstract
- While the demand for edge devices performing K-means clustering algorithm is expected to explode, this paper introduces a K-means clustering-specific processor for edge devices. The processor consists of hardware to accelerate the K-means algorithm and lightweight RISC-V core, and functional validation has been completed through RTL simulation and FPGA prototyping. The processor prototype demonstrates its excellence by performing the K-means algorithm about 56 times faster. © 2021 IEEE.
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