A Self-Triggered Digitally Assisted Hybrid LDO with 110 ns Settling Time in 65 nm CMOSopen access
- Authors
- Jin, Zhenbo; Kim, Gwangsub; Baek, Dong Hyun
- Issue Date
- Aug-2023
- Publisher
- MDPI
- Keywords
- hybrid; digitally assisted; low-dropout regulator (LDO); self-triggered; fast transient; low power
- Citation
- ELECTRONICS, v.12, no.15
- Journal Title
- ELECTRONICS
- Volume
- 12
- Number
- 15
- URI
- https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/67890
- DOI
- 10.3390/electronics12153215
- ISSN
- 2079-9292
2079-9292
- Abstract
- This article presents a self-triggered digitally assisted hybrid low-dropout regulator (LDO). The proposed architecture uses an analog LDO for steady-state operation and a digital LDO to track large output current changes. The dual loop has a loop controller for coherent operation, and the digital loop is only triggered when there is a large load step. Therefore, the proposed LDO inherits some of the advantages of both parts. It achieves a high power supply rejection ratio (PSRR) from the analog part. The digital loop has a faster settling time and consumes less static power than the analog loop. In this design, the maximum load is 200 mA. For heavy load conditions, PSRR is -40 dB at 1 MHz. The quiescent current is 200 & mu;A. The undershoot/overshoot with the corresponding settling time measured under a load current step of 200 mA/10 ns are 82 mV/89 ns and 112 mV/110 ns, respectively. The proposed LDO achieves a competitive 4.48 ps figure of merit. In the TSMC 65 nm process, the active area is approximately 0.027 mm(2).
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Collections - College of ICT Engineering > School of Electrical and Electronics Engineering > 1. Journal Articles
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