Florian: Developing a Low-Power RISC-V Multicore Processor with a Shared Lightweight FPU
- Authors
- Park, Jina; Han, Kyuseung; Choi, Eunjin; Lee, Sukho; Lee, Jae-Jin; Lee, Woojoo; Pedram, Massoud
- Issue Date
- Aug-2023
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Citation
- Proceedings of the International Symposium on Low Power Electronics and Design, v.2023-August
- Journal Title
- Proceedings of the International Symposium on Low Power Electronics and Design
- Volume
- 2023-August
- URI
- https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/70181
- DOI
- 10.1109/ISLPED58423.2023.10244431
- ISSN
- 1533-4678
- Abstract
- As applications running on lightweight RISC-V processors become increasingly diverse and complex, the need for multicore processors supporting floating-point units (FPUs) is riseing, making processor designs using existing open-source RISC-V cores challenging. With the exception of a very few, most open lightweight RISC-V cores are integer cores without FPUs, which greatly reduces the design exploration space, making it impossible to design a processor optimized for each application. For example, most of these applications mainly perform integer operations, but occasionally perform floating-point operations. For them, a multicore processor with FPU per core is overkill and wastes power, which is a critical problem for processors where low-power design is paramount. To address the problem, we propose an external lightweight FPU that can be attached to any RISC-V integer core and a low-power multicore architecture using the designed FPU. For verification, we designed a RISC-V processor that implements all the proposed technologies, prototyped it on an FPGA device, and finally fabricated it as a System-on-Chip. Through experiments, it was confirmed that the proposed technology can cut energy consumption energy by up to 23%. © 2023 IEEE.
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