Sub-10 nm Ge/GaAs Heterojunction-Based Tunneling Field-Effect Transistor with Vertical Tunneling Operation for Ultra-Low-Power Applications
DC Field | Value | Language |
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dc.contributor.author | Yoon, Young Jun | - |
dc.contributor.author | Seo, Jae Hwa | - |
dc.contributor.author | Cho, Seongjae | - |
dc.contributor.author | Kwon, Hyuck-In | - |
dc.contributor.author | Lee, Jung-Hee | - |
dc.contributor.author | Kang, In Man | - |
dc.date.available | 2019-03-08T13:36:35Z | - |
dc.date.issued | 2016-04 | - |
dc.identifier.issn | 1598-1657 | - |
dc.identifier.issn | 2233-4866 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/7117 | - |
dc.description.abstract | In this paper, we propose a sub-10 nm Ge/GaAs heterojunction-based tunneling field-effect transistor (TFET) with vertical band-to-band tunneling (BBT) operation for ultra-low-power (LP) applications. We design a stack structure that is based on the Ge/GaAs heterojunction to realize the vertical BBT operation. The use of vertical BBT operations in devices results in excellent subthreshold characteristics with a reduction in the drain-induced barrier thinning (DIBT) phenomenon. The proposed device with a channel length (L-ch) of 5 nm exhibits outstanding LP performance with a subthreshold swing (S) of 29.1 mV/dec and an off-state current (I-off) of 1.12 x 10(-11) A/mu m. In addition, the use of the high-k spacer dielectric HfO2 improves the on-state current (I-on) with an intrinsic delay time (tau) because of a higher fringing field. We demonstrate a sub-10 nm LP switching device that realizes a good S and lower Ioff at a lower supply voltage (V-DD) of 0.2 V. | - |
dc.format.extent | 7 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | IEEK PUBLICATION CENTER | - |
dc.title | Sub-10 nm Ge/GaAs Heterojunction-Based Tunneling Field-Effect Transistor with Vertical Tunneling Operation for Ultra-Low-Power Applications | - |
dc.type | Article | - |
dc.identifier.doi | 10.5573/JSTS.2016.16.2.172 | - |
dc.identifier.bibliographicCitation | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.16, no.2, pp 172 - 178 | - |
dc.identifier.kciid | ART002100859 | - |
dc.description.isOpenAccess | N | - |
dc.identifier.wosid | 000375763900006 | - |
dc.identifier.scopusid | 2-s2.0-84964816561 | - |
dc.citation.endPage | 178 | - |
dc.citation.number | 2 | - |
dc.citation.startPage | 172 | - |
dc.citation.title | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.citation.volume | 16 | - |
dc.type.docType | Article | - |
dc.publisher.location | 대한민국 | - |
dc.subject.keywordAuthor | Tunneling field-effect transistor (TFET) | - |
dc.subject.keywordAuthor | low-power (LP) performance | - |
dc.subject.keywordAuthor | short-channel effect (SCE) | - |
dc.subject.keywordAuthor | Ge/GaAs heterojunction | - |
dc.subject.keywordAuthor | vertical tunneling operation | - |
dc.subject.keywordPlus | PERFORMANCE | - |
dc.subject.keywordPlus | LOGIC | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.description.journalRegisteredClass | kci | - |
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