Thermally annealed asymmetric-offset polycrystalline thin film transistor with low leakage

Abstract

We have designed and fabricated a new top gate asymmetric offset structured n-type depletion mode poly-Si TFT of which the leakage current was considerably reduced due to successful suppression of electric field near the drain region caused by the asymmetric of et structure. The TFT was fabricated on the glass substrate by employing alternating magnetic field enhanced rapid thermal annealing (AMFERTA). The a-Si and n+ a-Si layers were deposited successively, and did not use any other ion doping methods. The asymmetric offset structure could be made without additional processes or masks. This new structure suppressed the leakage current to about 86% of non-offset structured AMFERTA poly-Si TFT without considerable sacrifice of on current. This suppression method of leak-age current can be helpful to remain the good image quality and save the power consumption Of AMOLED panels.