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A novel high performance junctionless FETs with saddle-gate
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Jin, Xiaoshi | - |
| dc.contributor.author | Wu, Meile | - |
| dc.contributor.author | Liu, Xi | - |
| dc.contributor.author | Chuai, Rongyan | - |
| dc.contributor.author | Kwon, Hyuck-In | - |
| dc.contributor.author | Lee, Jung-Hee | - |
| dc.contributor.author | Lee, Jong-Ho | - |
| dc.date.available | 2019-03-08T16:41:05Z | - |
| dc.date.issued | 2015-09 | - |
| dc.identifier.issn | 1569-8025 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/9142 | - |
| dc.description.abstract | In this paper, a novel junctionless field effect transistors (JL FETs) with a saddle-gate structure has been proposed, and the I-V characteristics has been extensively studied by TCAD device simulation. The performance comparison between saddle-gate JL FETs and conventional triple-gate JL FETs has also been performed. The influence of gate dielectric on device property has also been investigated. A scheme of design optimization of saddle-gate JL FETs has also been proposed. | - |
| dc.format.extent | 8 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.publisher | SPRINGER | - |
| dc.title | A novel high performance junctionless FETs with saddle-gate | - |
| dc.type | Article | - |
| dc.identifier.doi | 10.1007/s10825-015-0702-4 | - |
| dc.identifier.bibliographicCitation | JOURNAL OF COMPUTATIONAL ELECTRONICS, v.14, no.3, pp 661 - 668 | - |
| dc.description.isOpenAccess | N | - |
| dc.identifier.wosid | 000358655300002 | - |
| dc.identifier.scopusid | 2-s2.0-84938287209 | - |
| dc.citation.endPage | 668 | - |
| dc.citation.number | 3 | - |
| dc.citation.startPage | 661 | - |
| dc.citation.title | JOURNAL OF COMPUTATIONAL ELECTRONICS | - |
| dc.citation.volume | 14 | - |
| dc.type.docType | Article | - |
| dc.publisher.location | 미국 | - |
| dc.subject.keywordAuthor | Saddle-gate | - |
| dc.subject.keywordAuthor | Junctionless | - |
| dc.subject.keywordAuthor | Field effect transistors | - |
| dc.subject.keywordAuthor | Design optimization | - |
| dc.subject.keywordPlus | TRANSISTORS | - |
| dc.subject.keywordPlus | SIMULATION | - |
| dc.subject.keywordPlus | MOSFET | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.relation.journalResearchArea | Physics | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
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