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Modeling and analysis of III-V logic FETs for devices and circuits: Sub-22nm technology III-V SRAM cell design Go to Link

Oh, Saeroonter; Park, Jeongha; Wong, S. Simon; Wong, H.-S. Philip

ArticleIssue Date2010CitationProceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010, pp.342 - 346PublisherIEEE

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Browsing by Wong, H.-S. PhilipAuthor

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