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Modeling and analysis of III-V logic FETs for devices and circuits: Sub-22nm technology III-V SRAM cell design
- Issue Date
- Mar-2010
- Publisher
- IEEE
- Keywords
- Digital logic; Gate leakage current; High performance PMOS; III-V; Parasitic capacitance; SRAM
- Citation
- Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010, pp.342 - 346
- Indexed
- SCIE
SCOPUS
- Journal Title
- Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010
- Start Page
- 342
- End Page
- 346
- ISSN
- 1948-3287
- Abstract
- A compact model of III-V HFETs is developed for digital logic circuit applications such as a 6T-SRAM cell. We study sub-22nm technology III-V SRAM circuit design via III-V MOSFETs with thin high-k dielectric for low gate tunneling current, and optimized extrinsic structure for minimum parasitic capacitance. We investigate the drawbacks of a weak PMOS device in a SRAM cell and propose a minimum requirement for III-V PMOS strength for SRAM to be viable. ©2010 IEEE.
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