A 2.03-mW CMOS Image Sensor With an Integrated Four-Stacked Charge-Recycling Driver for Image Signal Transmissionopen access
- Authors
- Kim, Sang-Noon; Cho, Yongsung; Lee, Jiwon; Chun, Jung-Noon; Choi, Jaehyuk
- Issue Date
- Oct-2022
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- CMOS image sensor; correlated-multiple-sampling (CMS); dual-mode; low-power; power reduction techniques
- Citation
- IEEE Access, v.10, pp 99553 - 99561
- Pages
- 9
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE Access
- Volume
- 10
- Start Page
- 99553
- End Page
- 99561
- URI
- https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/112684
- DOI
- 10.1109/ACCESS.2022.3207298
- ISSN
- 2169-3536
- Abstract
- We propose a CMOS image sensor with a dedicated low-power imaging mode and low-power integrated transmitter. The proposed CMOS image sensor selectively operates in dual mode: a high-quality mode with a 1.5 V supply voltage of readout circuits to achieve a high signal-to-noise ratio (SNR), and a low-power mode with a 0.9 V supply voltage to support always-on imaging. To further reduce the power consumption in the low-power mode, a single-slope analog to digital converter (ADC) embeds a power cutoff scheme in the comparator and a two-step conversion with dual reference voltages. To alleviate the SNR degradation in the low-power mode, which inherently occurs from voltage scaling, a correlated multiple sampling technique that consumes negligible power overhead is implemented using the proposed window-counting scheme. To reduce the significant power consumption that occurs during image signal transmission, an integrated transmitter with four-stacked charge-recycling drivers is used so that four symbols are simultaneously transmitted with a shared supply voltage. A prototype CMOS image sensor with 680 x 520 pixels is fabricated using 110-nm CMOS image sensor technology. The fabricated CMOS image sensor consumes only 301 mu W (at 15 fps) in the sensor core and 2.03 mW including the transmitter and phase locked loop (PLL) while generating low temporal random noise under 0.27 LSB with correlated multiple sampling.
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Collections - COLLEGE OF SCIENCE AND CONVERGENCE TECHNOLOGY > DEPARTMENT OF PHOTONICS AND NANOELECTRONICS > 1. Journal Articles
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