A 2.5–5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection
- Authors
- Cho, Sung-Yong; Kim, Sungwoo; Choo, Min-Seong; Ko, Han-Gon; Lee, Jinhyung; Bae, Woorham; Jeong, Deog-Kyoon
- Issue Date
- Sep-2018
- Publisher
- Institute of Electrical and Electronics Engineers
- Keywords
- All-digital PLL (ADPLL); dual-edge injection; frequency detector; injection-locked oscillator (ILO); reference spur; sense-amplifier; sub-sampling PLL
- Citation
- IEEE Transactions on Circuits and Systems I: Regular Papers, v.65, no.9, pp 2691 - 2702
- Pages
- 12
- Indexed
- SCI
SCIE
SCOPUS
- Journal Title
- IEEE Transactions on Circuits and Systems I: Regular Papers
- Volume
- 65
- Number
- 9
- Start Page
- 2691
- End Page
- 2702
- URI
- https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/114259
- DOI
- 10.1109/TCSI.2018.2799195
- ISSN
- 1549-8328
1558-0806
- Abstract
- A 2.5-5.6 GHz low-phase-noise subharmonically injection-locked sub-sampling all-digital phase-locked loop with a dual-edge complementary switched injection technique is presented. While previously reported injection-locked phase-locked loops (ILPLLs) require additional circuitry for resolving a phase alignment mismatch between the PLL loop and injection path, the presented ILPLL exhibits a simplified architecture owing to the proposed injection technique and sub-sampling bang-bang phase detector (SSBBPD). Because the proposed injection technique exploits dual-edge injection, we analyze the performance impact of dual-edge injection when inaccurate injection timing occurs. This paper also offers an analysis of the injection technique based on the charge transfer and derives the realignment factor of the injection. With the proposed injection technique and the direct connection of the digitally controlled oscillator (DCO) clock to the SSBBPD, the timing mismatch between the PLL loop and injection path becomes insensitive to voltage and temperature drift. The proposed ILPLL prototype is fabricated in a 65-nm CMOS process and achieves a 168-fs integrated rms jitter over 1 kHz to 40 MHz at a 5-GHz output frequency with 156.25-MHz reference clock while consuming 15.4 mW with an active area of 0.06 mm2. © 2004-2012 IEEE.
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