A 285-fsrms Integrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Sungwoo | - |
dc.contributor.author | Jang, Sungchun | - |
dc.contributor.author | Cho, Sung-Yong | - |
dc.contributor.author | Choo, Min-Seong | - |
dc.contributor.author | Jeong, Gyu-Seob | - |
dc.contributor.author | Bae, Woorham | - |
dc.contributor.author | Jeong, Deog-Kyoon | - |
dc.date.accessioned | 2023-09-04T05:41:59Z | - |
dc.date.available | 2023-09-04T05:41:59Z | - |
dc.date.issued | 2016-12 | - |
dc.identifier.issn | 1598-1657 | - |
dc.identifier.issn | 2233-4866 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/114852 | - |
dc.description.abstract | An injection-locked ring phase-locked loop (ILRPLL) using a charge-stored complementary switch (CSCS) injection technique is described in this paper. The ILRPLL exhibits a wider lock range compared to other conventional ILRPLLs, owing to the improvement of the injection effect by the proposed CSCS. A frequency calibration loop and a device mismatch calibration loop force the frequency error to be zero to minimize jitter and reference spur. The prototype chip fabricated in 65-nm CMOS technology achieves a 285-fsrms integrated jitter at 3.328 GHz from the reference clock of 52 MHz while consuming 7.16 mW. The figure-of-merit of the ILRPLL is ‒242.4 dB. © 2016, Institute of Electronics Engineers of Korea. All rights reserved. | - |
dc.format.extent | 7 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | 대한전자공학회 | - |
dc.title | A 285-fsrms Integrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique | - |
dc.type | Article | - |
dc.publisher.location | 대한민국 | - |
dc.identifier.doi | 10.5573/JSTS.2016.16.6.860 | - |
dc.identifier.scopusid | 2-s2.0-85008324023 | - |
dc.identifier.wosid | 000393191400018 | - |
dc.identifier.bibliographicCitation | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.16, no.6, pp 860 - 866 | - |
dc.citation.title | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.citation.volume | 16 | - |
dc.citation.number | 6 | - |
dc.citation.startPage | 860 | - |
dc.citation.endPage | 866 | - |
dc.type.docType | 정기학술지(Article(Perspective Article포함)) | - |
dc.identifier.kciid | ART002175589 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.description.journalRegisteredClass | kci | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordPlus | LOW-POWER | - |
dc.subject.keywordPlus | OSCILLATOR | - |
dc.subject.keywordPlus | LOOP | - |
dc.subject.keywordAuthor | Charge-stored complementary switch (CSCS) | - |
dc.subject.keywordAuthor | Frequency synthesizer | - |
dc.subject.keywordAuthor | Injection-locked oscillator (ILO) | - |
dc.subject.keywordAuthor | Phase-locked loop (PLL) | - |
dc.identifier.url | https://koreascience.kr/article/JAKO201607959403082.page | - |
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