A 285-fsrms Integrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique
- Authors
- Kim, Sungwoo; Jang, Sungchun; Cho, Sung-Yong; Choo, Min-Seong; Jeong, Gyu-Seob; Bae, Woorham; Jeong, Deog-Kyoon
- Issue Date
- Dec-2016
- Publisher
- 대한전자공학회
- Keywords
- Charge-stored complementary switch (CSCS); Frequency synthesizer; Injection-locked oscillator (ILO); Phase-locked loop (PLL)
- Citation
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.16, no.6, pp 860 - 866
- Pages
- 7
- Indexed
- SCIE
SCOPUS
KCI
- Journal Title
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
- Volume
- 16
- Number
- 6
- Start Page
- 860
- End Page
- 866
- URI
- https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/114852
- DOI
- 10.5573/JSTS.2016.16.6.860
- ISSN
- 1598-1657
2233-4866
- Abstract
- An injection-locked ring phase-locked loop (ILRPLL) using a charge-stored complementary switch (CSCS) injection technique is described in this paper. The ILRPLL exhibits a wider lock range compared to other conventional ILRPLLs, owing to the improvement of the injection effect by the proposed CSCS. A frequency calibration loop and a device mismatch calibration loop force the frequency error to be zero to minimize jitter and reference spur. The prototype chip fabricated in 65-nm CMOS technology achieves a 285-fsrms integrated jitter at 3.328 GHz from the reference clock of 52 MHz while consuming 7.16 mW. The figure-of-merit of the ILRPLL is ‒242.4 dB. © 2016, Institute of Electronics Engineers of Korea. All rights reserved.
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