Flash ADC with Histogram-Driven F oreground Self-Calibration

Abstract

Flash analog to digital converters (ADCs) suffer significantly from their offset voltage variation in sub micron process technology, thereby lower linearity performance. This paper proposes an efficient flash ADC design method to calibrate the linearity error of flash ADC by wiggling comparators' offset based on histograms. Comparators with variable offset are employed, and their linearity errors can be analyzed and corrected (i.e., calibrated) based on the relationship between the integral nonlinearity (INL) and the ADC decision levels. The behavioral simulation results using an 8 bit ADC showed the DNL and the INL improved by 0.51 LSB and 1.86 LSB, respectively.