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BPPT - Bulk potential protection technique for hardened sequentials
- Authors
- Nofal, I; Evans, A.; He, A.-L.; Guo, G.; Li, Yuanqing; Chen, L.; Liu, R.; Wang, H.-B.; Chen, M.; Baeg, S.H.; Wen, S.-J.; Wong, R.
- Issue Date
- Jul-2017
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- Hardening; LET; Pass transistors; SER; Single event transient; Single event upset; Single events
- Citation
- 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017, pp 28 - 32
- Pages
- 5
- Indexed
- SCIE
SCOPUS
- Journal Title
- 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017
- Start Page
- 28
- End Page
- 32
- ISSN
- 0000-0000
1942-9401
- Abstract
- In this paper, we present a method for hardening memory and sequential cells against soft errors. The effect of the ionizing particle on the bulk potential is exploited to prevent the induced SET from propagating in the circuit. The proposed method requires a minimum number of extra transistors. The solution is applied to D Flip-Flop design, and alpha and heavy-ions test results are presented. © 2017 IEEE.
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Related Researcher
- Baeg, Sanghyeon
- ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)