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Simulation of a Recessed Channel Ferroelectric-Gate Field-Effect Transistor with a Dual Ferroelectric Gate Stack for Memory Application

Authors
김영현
Issue Date
15-Feb-2023
URI
https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/117553
Conference Name
한국반도체학술대회
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COLLEGE OF SCIENCE AND CONVERGENCE TECHNOLOGY > DEPARTMENT OF PHOTONICS AND NANOELECTRONICS > 2. Conference Papers

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COLLEGE OF SCIENCE AND CONVERGENCE TECHNOLOGY (DEPARTMENT OF PHOTONICS AND NANOELECTRONICS)
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