A 10-Bit Split-SAR ADC with Perturbation-based Background Digital Calibration

Abstract

It is hard to resolve the nonlinearity issue caused by the mismatch of bridge capacitor for split successive-approximation-resistor (SAR) analog-to-digital converters (ADCs). Furthermore, the nonlinearity introduced by capacitor mismatch in the SAR ADCs affects more series problem on the ADC performance. This paper proposes a design method of a split SAR-ADC with a background calibration to overcome both nonlinearities caused by the mismatches of a bridge capacitor as well as a binary-weighted capacitors. In this work, the same input signal is converted twice with additional capacitor, based on the perturbation manner. Then, the errors are calculated and those are alleviated in digital processing. The behavioral simulation results with the proposed 10bit split SAR ADC showed the enhanced DNL and INL as 0.69LSB and 0.75LSB, respectively. The SNDR and SFDR are improved by 4.72dB and 6.3dB, respectively.