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The Generalization of Stage-Reduced STPS for Low-Loss Unequal 1×4 Phased Array Architecture for 5G IoT Applications

Authors
Lee, Ahn wooKim, Sung hyukLee, Dong minKim, Jung hyunJang, Tae Hwan
Issue Date
Jun-2024
Publisher
Institute of Electrical and Electronics Engineers Inc.
Keywords
0.15-μm GaAs pHEMT; 5G mobile communication; Antenna radiation patterns; beamforming; Dipole antennas; Insertion loss; Internet of Things; Ka-band; low loss; mm-Wave circuits; phase shifter; Phase shifters; Phased arrays; phased-array
Citation
IEEE Internet of Things Journal, v.11, no.11, pp 1 - 10
Pages
10
Indexed
SCIE
SCOPUS
Journal Title
IEEE Internet of Things Journal
Volume
11
Number
11
Start Page
1
End Page
10
URI
https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/118917
DOI
10.1109/JIOT.2024.3367902
ISSN
2327-4662
Abstract
In this work, the stage-reduced switched type phase shifter (STPS) based low loss and unequal phased array architecture without any power consumption is presented for 5G IoT application. Since phase difference between channels (β) in β ≤ -90∘ and β ≥ 90∘ range is rarely used in practice because the side-lobe of the antenna increases, phase shifter units are unequally designed for each channel so as to use only the -90∘ ≤ β ≤ 90∘ region, which is a region with a small side-lobe. In practice, this stage-reduced STPS structure is generalized to be applied to n-stage 1×4 beamforming architecture. As an example, a 4-bits conventional phase shifter with 22.5∘ resolution is implemented using only 3-bits in 0.15-μm GaAs pHEMT for 28GHz 5G n257 band. Compared to the conventional structure, insertion loss is improved thanks to removing 0∘/180∘ stage revealing the highest insertion loss among the conventional 4 stages. The measured average insertion loss of the stage-reduced STPS is -4.3 dB and -3.2 dB for channels 1 and 4, and channels 2 and 3, respectively. The side-lobe of the proposed phased array is also improved as much as 1.6 dB than that of conventional phased array architecture since the insertion loss of channels 1 and 4 located on the edge side is 1.1 dB higher than that of channels 2 and 3. The proposed stage-reduced STPS reveals figure of merit lower than -1 dB without using any power consumption. To the best of our knowledge, this STPS achieves the lowest insertion loss among the published GaAs/CMOS STPS over a similar frequency.
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Jang, Taehwan
ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)
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