TCAD simulation study of dual ferroelectric gate field-effect transistors with a recessed channel geometry for non-volatile memory applications
- Authors
- Chen, Simin; Ahn, Dae-Hwan; An, Seong Ui; Noh, Tae Hyeon; Kim, Younghyun
- Issue Date
- May-2024
- Publisher
- Korean Physical Society
- Keywords
- Ferroelectric FETs (FeFETs); MFMIS; Recessed channel
- Citation
- Journal of the Korean Physical Society, pp 1 - 9
- Pages
- 9
- Indexed
- SCIE
SCOPUS
KCI
- Journal Title
- Journal of the Korean Physical Society
- Start Page
- 1
- End Page
- 9
- URI
- https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/119196
- DOI
- 10.1007/s40042-024-01079-7
- ISSN
- 0374-4884
1976-8524
- Abstract
- In this study, we propose a ferroelectric FET (FeFET) structure termed dual ferroelectric recessed channel FeFET (DF-RFeFET), employing metal–ferroelectric (FE)–metal–FE–metal–SiO2 interlayer (IL)–silicon (MFMFMIS) structures. The DF-RFeFET is aimed at enhancing the memory window (MW) for high-performance memory applications. TCAD simulations with calibrated FE parameters and device models reveal that the DF-RFeFET can achieve a larger MW thanks to the enhanced geometric advantage to offer a strong and localized electric field at the inner ferroelectrics near the gate metal’s corner. Moreover, design guidelines for the DF-RFeFET are suggested, including adjusting the inner and outer ferroelectric layers' thickness ratio and the recessed channel depth. The effects of introducing a relatively low-k oxide intermediate layer between dual ferroelectric layers and high-k gate stacks of IL on the MW have also been investigated. Through structural optimization, the DF-RFeFET demonstrated a record MW value of 5.5 V among the previously reported Si FeFETs. © The Korean Physical Society 2024.
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