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Optimizing Length Scalability of InGaZnO Thin-Film Transistors through Lateral Carrier Profile Engineering and Negative Δ<i>L</i> Extension Structureopen access

Authors
Kim, Su HyunKim, MingooLee, Ji HwanKim, KihwanPark, Joon SeokLim, Jun HyungOh, Saeroonter
Issue Date
Jun-2024
Publisher
Wiley-VCH Verlag
Keywords
carrier profile engineering; carrier profile extraction; gate insulator shoulder; length scalability; negative Delta L extension; oxide semiconductor
Citation
Advanced Electronic Materials, pp 1 - 6
Pages
6
Indexed
SCIE
SCOPUS
Journal Title
Advanced Electronic Materials
Start Page
1
End Page
6
URI
https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/119891
DOI
10.1002/aelm.202400012
ISSN
2199-160X
Abstract
The lateral carrier profile of amorphous indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) plays a significant role in determining the effective channel length (L-eff) and length scalability even when the physical gate length (L-g) is the same. Especially, devices with high carrier concentration that have a high mobility of 14.54 cm(2) V<middle dot>s(-1) suffer from severe short channel effects at L-g = 1 mu m due to the reduced L-eff. The current work proposes a systematic methodology for optimizing length scalability for a given L-g that involves engineering of the lateral carrier profile. Unique lateral carrier profiles are extracted using contour maps of Delta L and R-SD as a function of carrier profile parameters, and they are validated by comparing the measured L-eff, drain-to-source resistance, and current-voltage characteristics with the results of simulations using the extracted carrier profiles. Further, to overcome the trade-off between enhanced mobility and degraded V-T roll-off that occurs with increasing carrier concentration, an IGZO TFT with gate-insulator shoulders is fabricated to structurally form negative Delta L and physically increase L-eff, while also obtaining a high carrier concentration, ultimately achieving both optimal electrical performance, with mobility of 17.50 cm(2) V<middle dot>s(-1), and complete control of the electrostatic integrity of the gate.
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ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)
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