A 65 nm Temporally Hardened Flip-Flop Circuit

Abstract

A guard-gate based flip-flop circuit temporally hardened against single-event effects is presented in this paper. Compared to several existed techniques, the organization of components inside the proposed design allows the improved performance- only one tau (the maximum width of a single-event transient (SET) to tolerate) is added into the setup time. A previously reported low-power delay element is applied, which helps make the proposed design power-efficient. The proposed design was implemented in a 65 nm CMOS bulk technology. Alpha and heavy-ions radiation experiments were performed to characterize its soft-error rates. Experimental results show that the proposed design presents no error with LETs up to 37.3 MeV-cm(2)/mg. Simulation results from the TFIT further validate the experimental results.