A 65 nm Temporally Hardened Flip-Flop Circuit
- Authors
- Li, Y. -Q.; Wang, H. -B.; Liu, Rui; Chen, Li; Nofal, Issam; Chen, Q. -Y.; He, A. -L.; Guo, Gang; Baeg, Sang H.; Wen, Shi-Jie; Wong, Richard; Wu, Qiong; Chen, Mo
- Issue Date
- Dec-2016
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Flip-flop; SET; SEU; temporal hardening
- Citation
- IEEE TRANSACTIONS ON NUCLEAR SCIENCE, v.63, no.6, pp.2934 - 2940
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON NUCLEAR SCIENCE
- Volume
- 63
- Number
- 6
- Start Page
- 2934
- End Page
- 2940
- URI
- https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/12184
- DOI
- 10.1109/TNS.2016.2608911
- ISSN
- 0018-9499
- Abstract
- A guard-gate based flip-flop circuit temporally hardened against single-event effects is presented in this paper. Compared to several existed techniques, the organization of components inside the proposed design allows the improved performance- only one tau (the maximum width of a single-event transient (SET) to tolerate) is added into the setup time. A previously reported low-power delay element is applied, which helps make the proposed design power-efficient. The proposed design was implemented in a 65 nm CMOS bulk technology. Alpha and heavy-ions radiation experiments were performed to characterize its soft-error rates. Experimental results show that the proposed design presents no error with LETs up to 37.3 MeV-cm(2)/mg. Simulation results from the TFIT further validate the experimental results.
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Collections - COLLEGE OF ENGINEERING SCIENCES > SCHOOL OF ELECTRICAL ENGINEERING > 1. Journal Articles
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