칩내 배선의 RC/RLC 모델의 정확성 검증

Abstract

The RC/RLC models for on chip interconnect lines are experimentally investigated. The signal transient of the RC model does not match with that of S-parameter. The RC model overestimates the eye height in 40% and underestimates the jitter in 20%. Thereby, it is reported that the high performance system design using RC model may result in serious design errors. In order to improve the system performance, the pre-emphasis circuit is proposed and its performances are verified with simulation. The proposed circuit achieves much better performance in terms of eye height and jitter. The proposed circuit provides eye opening enough to capture the input signal up to 8.5Gbps.