Time-multiplexed test access architecture for stacked integrated circuits
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Ansari, Muhammad Adil | - |
dc.contributor.author | Jung, Jihun | - |
dc.contributor.author | Kim, Dooyoung | - |
dc.contributor.author | Park, Sungju | - |
dc.date.accessioned | 2021-06-22T16:24:09Z | - |
dc.date.available | 2021-06-22T16:24:09Z | - |
dc.date.created | 2021-01-21 | - |
dc.date.issued | 2016-07 | - |
dc.identifier.issn | 1349-2543 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/13148 | - |
dc.description.abstract | Due to ever-increasing gap between (1) the tester-channel and scan-shift frequencies, and (2) the wafer-level and package-level test frequencies, the tester-channel frequency is underutilized for stacked-ICs. Thus, we present a novel time-multiplexed test access architecture for SICs that complies with P1838 and it significant reduces test time, which reduction is observed on a synthetic SIC based on ITC'02 benchmark SoCs. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG | - |
dc.title | Time-multiplexed test access architecture for stacked integrated circuits | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Park, Sungju | - |
dc.identifier.doi | 10.1587/elex.13.20160314 | - |
dc.identifier.scopusid | 2-s2.0-84979518445 | - |
dc.identifier.wosid | 000381574500001 | - |
dc.identifier.bibliographicCitation | IEICE ELECTRONICS EXPRESS, v.13, no.14, pp.1 - 6 | - |
dc.relation.isPartOf | IEICE ELECTRONICS EXPRESS | - |
dc.citation.title | IEICE ELECTRONICS EXPRESS | - |
dc.citation.volume | 13 | - |
dc.citation.number | 14 | - |
dc.citation.startPage | 1 | - |
dc.citation.endPage | 6 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | Y | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | OPTIMIZATION | - |
dc.subject.keywordAuthor | 3D test access architecture | - |
dc.subject.keywordAuthor | design-for-testability | - |
dc.subject.keywordAuthor | stacked-ICs | - |
dc.identifier.url | https://www.jstage.jst.go.jp/article/elex/13/14/13_13.20160314/_article | - |
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