Efficient Low-power Scan Test Method based on Exclusive Scan and Scan Chain Reordering

Abstract

With advancements in process technology and ever-increasing complexity of digital circuits, testing has become a prominent problem. The lengthy scan chains used for testing semiconductor chips cause not only the longer test time but also excessive test power consumption. Such excessive test power (especially peak power during shifting) can cause reliability degradation for the semiconductor. To resolve this problem, we introduce an exclusive shift-in and shift-out method along with a scan chain reordering algorithm. The proposed method is evaluated with several benchmark circuits including ISCAS’89, ITC’99 and IWLS’05. The results indicate that the proposed technique reduces the average power and helps mitigating the peak power consumption. In addition, an optimization method is introduced to reduce the area overhead of proposed scan technique. As a result, area overhead of proposed scan architecture was reduced to 1-11%.