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Quantifying the Risk Level of Functional Chips in DRAM Wafers
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Jeong, Young-Seon | - |
| dc.contributor.author | Kim, Byunghoon | - |
| dc.contributor.author | Tong, Seung Hoon | - |
| dc.contributor.author | Chang, In-Kap | - |
| dc.contributor.author | Jeong, Myong K. | - |
| dc.date.accessioned | 2021-06-22T18:43:27Z | - |
| dc.date.available | 2021-06-22T18:43:27Z | - |
| dc.date.created | 2021-02-18 | - |
| dc.date.issued | 2015-11 | - |
| dc.identifier.issn | 1541-1672 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/16534 | - |
| dc.language | 영어 | - |
| dc.language.iso | en | - |
| dc.publisher | IEEE COMPUTER SOC | - |
| dc.title | Quantifying the Risk Level of Functional Chips in DRAM Wafers | - |
| dc.type | Article | - |
| dc.contributor.affiliatedAuthor | Kim, Byunghoon | - |
| dc.identifier.bibliographicCitation | IEEE INTELLIGENT SYSTEMS, v.30, no.6, pp.21 - 24 | - |
| dc.relation.isPartOf | IEEE INTELLIGENT SYSTEMS | - |
| dc.citation.title | IEEE INTELLIGENT SYSTEMS | - |
| dc.citation.volume | 30 | - |
| dc.citation.number | 6 | - |
| dc.citation.startPage | 21 | - |
| dc.citation.endPage | 24 | - |
| dc.type.rims | ART | - |
| dc.description.journalClass | 1 | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.identifier.url | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7320917 | - |
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Related Researcher
- Kim, Byunghoon
- ERICA 공학대학 (DEPARTMENT OF INDUSTRIAL & MANAGEMENT ENGINEERING)