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Quantifying the Risk Level of Functional Chips in DRAM Wafers
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Jeong, Young-Seon | - |
| dc.contributor.author | Kim, Byunghoon | - |
| dc.contributor.author | Tong, Seung Hoon | - |
| dc.contributor.author | Chang, In-Kap | - |
| dc.contributor.author | Jeong, Myong K. | - |
| dc.date.accessioned | 2021-06-22T18:43:27Z | - |
| dc.date.available | 2021-06-22T18:43:27Z | - |
| dc.date.issued | 2015-11 | - |
| dc.identifier.issn | 1541-1672 | - |
| dc.identifier.issn | 1941-1294 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/16534 | - |
| dc.format.extent | 4 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.publisher | Institute of Electrical and Electronics Engineers | - |
| dc.title | Quantifying the Risk Level of Functional Chips in DRAM Wafers | - |
| dc.type | Article | - |
| dc.publisher.location | 미국 | - |
| dc.identifier.wosid | 000365030200007 | - |
| dc.identifier.bibliographicCitation | IEEE Intelligent Systems, v.30, no.6, pp 21 - 24 | - |
| dc.citation.title | IEEE Intelligent Systems | - |
| dc.citation.volume | 30 | - |
| dc.citation.number | 6 | - |
| dc.citation.startPage | 21 | - |
| dc.citation.endPage | 24 | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | sci | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Computer Science | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.relation.journalWebOfScienceCategory | Computer Science, Artificial Intelligence | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
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Related Researcher
- Kim, Byunghoon
- ERICA 공학대학 (DEPARTMENT OF INDUSTRIAL & MANAGEMENT ENGINEERING)