A 10-bit 200-MS/s Zero-Crossing-Based Pipeline ADC in 0.13-mu m CMOS Technology
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chu, Myonglae | - |
dc.contributor.author | Kim, Byoungho | - |
dc.contributor.author | Lee, Byung-Geun | - |
dc.date.accessioned | 2021-06-22T18:44:07Z | - |
dc.date.available | 2021-06-22T18:44:07Z | - |
dc.date.created | 2021-01-21 | - |
dc.date.issued | 2015-11 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/16571 | - |
dc.description.abstract | This brief presents a zero-crossing-based pipeline analog-to-digital converter (ADC) architecture that can effectively reduce hardware complexity and power consumption for high-speed ADCs. The ADC uses only simple open-loop amplifiers for residue amplification. Using modified sliding interpolation and subranging techniques, the number of amplifiers is reduced by 60%. A 10-bit 200-MS/s ADC, employing the architecture and other techniques, such as double sampling, digital error correction, and source degeneration, is fabricated in 0.13-mu m CMOS process and occupies a die area of 0.7 mm(2). The differential and integral nonlinearity of the ADC are less than 0.83/-0.47 and 1.05/-0.7 LSB, respectively. With a 1.5-MHz full-scale input, the ADC achieves 56.5-dB signal-to-noise plus distortion ratio, 71.8-dB spurious free dynamic range, and 9.1 effective number of bits at full sampling rate while dissipating 38 mW from a 1.2-V supply. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A 10-bit 200-MS/s Zero-Crossing-Based Pipeline ADC in 0.13-mu m CMOS Technology | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Byoungho | - |
dc.identifier.doi | 10.1109/TVLSI.2014.2371453 | - |
dc.identifier.scopusid | 2-s2.0-84914811556 | - |
dc.identifier.wosid | 000364209000028 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.23, no.11, pp.2671 - 2675 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.title | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.volume | 23 | - |
dc.citation.number | 11 | - |
dc.citation.startPage | 2671 | - |
dc.citation.endPage | 2675 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | A/D CONVERTER | - |
dc.subject.keywordPlus | DISTORTION | - |
dc.subject.keywordAuthor | Analog-to-digital converter (ADC) | - |
dc.subject.keywordAuthor | digital error correction | - |
dc.subject.keywordAuthor | interpolation | - |
dc.subject.keywordAuthor | open-loop (OL) amplifier | - |
dc.subject.keywordAuthor | pipeline ADC | - |
dc.subject.keywordAuthor | zero-crossing detection | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/6975192 | - |
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