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Hybrid Test Data Transportation Scheme for Advanced NoC-Based SoCs

Authors
M. Adil AnsariDooyoung KimJihun Jung박성주
Issue Date
Feb-2015
Publisher
대한전자공학회
Keywords
Packet multicast; network on chip; scan test
Citation
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.15, no.1, pp.85 - 95
Indexed
SCIE
SCOPUS
KCI
Journal Title
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
Volume
15
Number
1
Start Page
85
End Page
95
URI
https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/20195
DOI
10.5573/JSTS.2015.15.1.085
ISSN
1598-1657
Abstract
Network-on-chip (NoC) has evolved to overcome the issues of traditional bus-based on-chip interconnect. In NoC-reuse as TAM, the test schedulers are constrained with the topological position of cores and test access points, which may negatively affect the test time. This paper presents a scalable hybrid test data transportation scheme that allows to simultaneously test multiple heterogeneous cores of NoC-based SoCs, while reusing NoC as TAM. In the proposed test scheme, single test stimuli set of multiple CUTs is embedded into each flit of the test stimuli packets and those packets are multicast to the targeted CUTs. However, the test response packets of each CUT are unicast towards the tester. To reduce network load, a flit is filled with maximum possible test response sets before unicasting towards the tester. With the aid of Verilog and analytical simulations, the proposed scheme is proved effective and the results are compared with some recent techniques.
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