Architectural design tradeoffs in SRAM-based TCAMs

Abstract

An SRAM-based TCAM (SbT) memory architecture is proposed which exploits the tradeoffs among critical design parameters - such as throughput (T), latency (L), SRAM utilization (U), and power dissipation (P). An 18 kb TCAM is implemented on FPGA that can be adapted as latency & throughput efficient (LTE), Mid-efficient (ME), or a power & memory efficient (PME). Our implementation results show that LTE utilizes 79.3% and 96.5% more SRAM bit resources, consumes 45% and 55% more dynamic power than the ME and the PME, respectively. However, the LTE architecture shows an efficient single clock cycle latency and higher throughput than ME and PME, respectively.