Impact of III-V and Ge Devices on Circuit Performance
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, Jeongha | - |
dc.contributor.author | Oh, Saeroonter | - |
dc.contributor.author | Kim, SoYoung | - |
dc.contributor.author | Wong, H. -S. Philip | - |
dc.contributor.author | Wong, S. Simon | - |
dc.date.accessioned | 2021-06-23T03:03:14Z | - |
dc.date.available | 2021-06-23T03:03:14Z | - |
dc.date.created | 2021-01-21 | - |
dc.date.issued | 2013-07 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/27548 | - |
dc.description.abstract | III-V and germanium (Ge) field-effect transistors (FETs) have been studied as candidates for post Si CMOS. In this paper, the performance of various digital blocks and static random access memory (SRAM) with different combinations of Si, III-V and Ge devices are studied. SPICE-compatible III-V n-channel FET (nFET) and Ge p-channel FET (pFET) models are developed for the analysis. The delay and energy of the different combinations are estimated and compared. In typical digital design, the driving capability of the nFET and pFET should be matched for optimum noise margin and performance. The combination of III-V nFET with low input capacitance and Ge pFET achieves the best energy-delay performance for many digital logic circuits. The read margin of SRAM is maximized with a Si pass-gate, and an inverter of III-V nFET and Ge pFET. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Impact of III-V and Ge Devices on Circuit Performance | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Oh, Saeroonter | - |
dc.identifier.doi | 10.1109/TVLSI.2012.2210450 | - |
dc.identifier.scopusid | 2-s2.0-84880056520 | - |
dc.identifier.wosid | 000320946200002 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.21, no.7, pp.1189 - 1200 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.title | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.volume | 21 | - |
dc.citation.number | 7 | - |
dc.citation.startPage | 1189 | - |
dc.citation.endPage | 1200 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | MOSFET | - |
dc.subject.keywordPlus | ARCHITECTURE | - |
dc.subject.keywordAuthor | Adder | - |
dc.subject.keywordAuthor | digital logic circuit | - |
dc.subject.keywordAuthor | field-programmable gate array (FPGA) | - |
dc.subject.keywordAuthor | germanium (Ge) | - |
dc.subject.keywordAuthor | III-V | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/6289382 | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
55 Hanyangdeahak-ro, Sangnok-gu, Ansan, Gyeonggi-do, 15588, Korea+82-31-400-4269 sweetbrain@hanyang.ac.kr
COPYRIGHT © 2021 HANYANG UNIVERSITY. ALL RIGHTS RESERVED.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.