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Memory Test Strategies in SoC (Embedded Memories)
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 백상현 | - |
| dc.date.accessioned | 2021-06-23T03:47:26Z | - |
| dc.date.available | 2021-06-23T03:47:26Z | - |
| dc.date.issued | 2006-06-30 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/28531 | - |
| dc.description.abstract | Introduction Quality Different stages of memory test BIST Test Examples and Results Other perspectives Conclusions | - |
| dc.title | Memory Test Strategies in SoC (Embedded Memories) | - |
| dc.type | Conference | - |
| dc.citation.conferenceName | 한국 테스트 학술대회 | - |
| dc.citation.conferencePlace | 서울교육문화회관 별관 3층 동강홀 | - |
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Related Researcher
- Baeg, Sanghyeon
- ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)