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Extraction Technique for Intrinsic Subgap DOS in a-IGZO TFTs by De-Embedding the Parasitic Capacitance Through the Photonic C-V Measurement

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dc.contributor.authorBae, Hagyoul-
dc.contributor.authorChoi, Hyunjun-
dc.contributor.authorOh, Saeroonter-
dc.contributor.authorKim, Dae Hwan-
dc.contributor.authorBae, Jonguk-
dc.contributor.authorKim, Jaehyeong-
dc.contributor.authorKim, Yun Hyeok-
dc.contributor.authorKim, Dong Myong-
dc.date.accessioned2021-06-23T04:22:25Z-
dc.date.available2021-06-23T04:22:25Z-
dc.date.created2021-01-21-
dc.date.issued2013-01-
dc.identifier.issn0741-3106-
dc.identifier.urihttps://scholarworks.bwise.kr/erica/handle/2021.sw.erica/29227-
dc.description.abstractWe report a technique for extraction of the intrinsic subgap density of states (gA,(int)(E)) by deembedding the parasitic capacitance in amorphous indium-gallium-zinc-oxide TFTs through the optical charge pumping method. As structure-dependent parameters in the proposed extraction technique, the overlap length L-ov between the source/drain (S/D) and the active layer and the parasitic overlap area between the gate and the S/D metal (C-par,C-S/C-par,C-D) are considered under dark and subbandgap photonic states. We obtained g(A,int)(E) as a superposition of the exponential deep and tail states with N-TA,N-int = 6.0x10(16) eV(-1) . cm(-3), kT(TA,int) = 0.16 eV, N-DA,N-int = 1.8 x 10(15) eV(-1) . cm(-3), and kT(DA,int) = 1.9 eV from samples with various parasitic areas.-
dc.language영어-
dc.language.isoen-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleExtraction Technique for Intrinsic Subgap DOS in a-IGZO TFTs by De-Embedding the Parasitic Capacitance Through the Photonic C-V Measurement-
dc.typeArticle-
dc.contributor.affiliatedAuthorOh, Saeroonter-
dc.identifier.doi10.1109/LED.2012.2222014-
dc.identifier.scopusid2-s2.0-84871748017-
dc.identifier.wosid000312834200019-
dc.identifier.bibliographicCitationIEEE ELECTRON DEVICE LETTERS, v.34, no.1, pp.57 - 59-
dc.relation.isPartOfIEEE ELECTRON DEVICE LETTERS-
dc.citation.titleIEEE ELECTRON DEVICE LETTERS-
dc.citation.volume34-
dc.citation.number1-
dc.citation.startPage57-
dc.citation.endPage59-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlusFRINGE CAPACITANCE-
dc.subject.keywordAuthorAmorphous-
dc.subject.keywordAuthorextraction-
dc.subject.keywordAuthoroverlap capacitance-
dc.subject.keywordAuthorparasitic capacitance-
dc.subject.keywordAuthorparasitic effect-
dc.subject.keywordAuthorsubgap density of states (DOS)-
dc.subject.keywordAuthorthin-film transistors (TFTs)-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/6361260/-
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ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)
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