Efficient performance evaluation of high-speed differential interconnect lines with via discontinuities
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Hyewon | - |
dc.contributor.author | Lee, Junghyun | - |
dc.contributor.author | Eo, Yungseon | - |
dc.date.accessioned | 2021-06-23T05:24:54Z | - |
dc.date.available | 2021-06-23T05:24:54Z | - |
dc.date.issued | 2013-10 | - |
dc.identifier.issn | 2165-4107 | - |
dc.identifier.issn | 2165-4115 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/30572 | - |
dc.description.abstract | Vias in transmission lines cause significant waveform distortion due to electromagnetic wave reflections and vias may behavior like a band rejection filter due to resonances in between reference planes. These undesirable effects significantly exacerbate the signal integrity in high-speed and high-frequency integrated circuits, packaged modules, or printed circuit board (PCB). In this work, discontinuous interconnect lines including vias are experimentally characterized with S-parameter measurements in the frequency range of 10 MHz to 40 GHz. Then base on the experimental characterizations, an accurate circuit model to represent electrical characteristics of the vias is developed. It is shown that with the proposed technique, the high-performance integrated system can be efficiently designed by avoiding the conventional strict layout design rules for the discontinuous lines. © 2013 IEEE. | - |
dc.format.extent | 4 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | IEEE Computer Society | - |
dc.title | Efficient performance evaluation of high-speed differential interconnect lines with via discontinuities | - |
dc.type | Article | - |
dc.publisher.location | 미국 | - |
dc.identifier.doi | 10.1109/EPEPS.2013.6703500 | - |
dc.identifier.scopusid | 2-s2.0-84893612963 | - |
dc.identifier.bibliographicCitation | 2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013, pp 207 - 210 | - |
dc.citation.title | 2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013 | - |
dc.citation.startPage | 207 | - |
dc.citation.endPage | 210 | - |
dc.type.docType | Conference Paper | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | other | - |
dc.subject.keywordPlus | Circuit simulation | - |
dc.subject.keywordPlus | Resonance | - |
dc.subject.keywordPlus | Scattering parameters | - |
dc.subject.keywordPlus | Circuit modeling | - |
dc.subject.keywordPlus | Electrical characteristic | - |
dc.subject.keywordPlus | Experimental characterization | - |
dc.subject.keywordPlus | Printed circuit boards (PCB) | - |
dc.subject.keywordPlus | S-Parameter measurements | - |
dc.subject.keywordPlus | Signal Integrity | - |
dc.subject.keywordPlus | vias | - |
dc.subject.keywordPlus | Waveform distortions | - |
dc.subject.keywordPlus | Electronics packaging | - |
dc.subject.keywordAuthor | Circuit model | - |
dc.subject.keywordAuthor | resonance | - |
dc.subject.keywordAuthor | scattering parameters | - |
dc.subject.keywordAuthor | signal integrity | - |
dc.subject.keywordAuthor | vias | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/6703500 | - |
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